You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Suppose I have a verilog file with modules and lots of sub modules and also with pins inside the submodule.
I want to display the whole address of the pin or port input by user
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-14T01:14:39Z
This is not supported by vhier, and is unlikely to be added in the future, sorry. To do this you'd need to write your own perl program that uses the Verilog::Netlist package.
Author Name: Utkarsh Khanna
Original Redmine Issue: 1463 from https://www.veripool.org
Original Assignee: Utkarsh Khanna
Suppose I have a verilog file with modules and lots of sub modules and also with pins inside the submodule.
I want to display the whole address of the pin or port input by user
The text was updated successfully, but these errors were encountered: