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Constant function evaluator incorrect on return of function var #1467

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veripoolbot opened this issue Jun 15, 2019 · 3 comments
Closed

Constant function evaluator incorrect on return of function var #1467

veripoolbot opened this issue Jun 15, 2019 · 3 comments
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed

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@veripoolbot
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Author Name: Roman Popov
Original Redmine Issue: 1467 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Trying to debug the root cause of multiple errors. Here is a minimal example I've managed to extract:

module dut #(
     parameter DEPTH = 16,
     parameter WIDTH = 32,
     parameter RAM_SPLIT_WIDTH = 16
)
(
     output logic [WIDTH-1:0] ram_dataout
);

localparam RAM_ADDR_WIDTH = $clog2(DEPTH);
localparam NUM_RAM_BLOCKS = WIDTH/RAM_SPLIT_WIDTH + (WIDTH%RAM_SPLIT_WIDTH > 0);
typedef logic [NUM_RAM_BLOCKS:0][31:0] block_index_t;

function automatic block_index_t index_calc(input int WIDTH, NUM_RAM_BLOCKS);
     index_calc[0] = '0;
     for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = WIDTH/NUM_RAM_BLOCKS + (i < (WIDTH%NUM_RAM_BLOCKS));
     for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = index_calc[i+1] + index_calc[i];
     return index_calc;
endfunction

localparam block_index_t RAM_BLOCK_INDEX = index_calc(WIDTH, NUM_RAM_BLOCKS);

generate
     begin : ram_dataout_gen
         for (genvar i = 0; i < NUM_RAM_BLOCKS; i++) begin
                 always_comb ram_dataout[RAM_BLOCK_INDEX[i+1]-1:RAM_BLOCK_INDEX[i]] = 0;
         end
     end
endgenerate

endmodule

module top (
     input clk,
     output logic [31:0] ram_dataout    
);

dut dut0(.*);

endmodule
</code>
%Warning-WIDTH: top.sv:11: Operator ADD expects 32 or 6 bits on the RHS, but RHS's GTS generates 1 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: top.sv:16: Operator ADD expects 32 bits on the RHS, but RHS's LTS generates 1 bits.
%Error: top.sv:26: [-1:0] Range extract has backward bit ordering, perhaps you wanted [0:-1]

So Verilator incorrectly evaluates RAM_BLOCK_INDEX[1] to 0.
Works fine in VCS/DC.

verilator --lint-only -sv -top-module top top.sv

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-15T02:56:41Z


Well, this one is entertaining. Basically this:

   return index_calc;

The function is already using index_calc as the variable, so this return which should be trivial hits a bug.

Will get to a fix shortly, but you can comment out the return for the moment.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-15T12:10:26Z


Thanks for the good test case.

Fixed in git towards 4.015.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-16T13:59:53Z


In 4.016.

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Labels
area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed
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