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Issue #1472

Memory not updating in for loop

Added by Somya Dashora 4 months ago. Updated 12 days ago.

Status:
NotEnoughInfo
Priority:
High
Assignee:
-
Category:
WrongRuntimeResult
% Done:

0%


Description

We are facing an issue with following verilog code

Snippets of the relevant portion of code is shown below :


module DUT (

            //signal declaration

            ) ;

input Clear_Signal;
input rst ;
reg [3:0] Dist_Ram [ 0 : RAM_DEPTH ] ;

integer i;

    always @ ( posedge clk )
       begin
           if ( !rst )
          begin
             for( i=0 ; i < RAM_DEPTH ; i=i+1 ) // reset RAM with zeros
                Dist_Ram [ i ] <= {  4{ 1'b0 } };
             end

            else
              begin
                 if ( Clear_Signal )                                       
                   begin
                      for ( i=0 ; i < RAM_DEPTH ; i = i+1 )
                                Dist_Ram [ i ] <= 4'd0 ;
                   end

               // ---- Some Code Followed . . .
               .
               .
               .
               .
               .

endmodule

The problem i am facing is that when signal Clear_Signal is asserted the Dist_Ram should have all zero as it content.

But on displaying the content we get

Dist_Ram[0] = 1001  // Some data written 
Dist_Ram[1] = 1011  // by some code
Dist_Ram[2] = 1010  // 
.
.
.
.
.
Dist_Ram[9] = 1001

This in not as expected.

However the same code on Questa Sim-64 Version 10.6a results in

Dist_Ram[0] = 0000
Dist_Ram[1] = 0000
Dist_Ram[2] = 0000
.
.
.
.
.
Dist_Ram[9] = 0000

Which is desired and expected.

We think this might be due the common loop variable 'i' which we are using to unroll the for loop - in both cases of rst and Clear_Signal.

The verilator version on which the code was run is :

Verilator 4.016 2019-06-16 rev UNKNOWN_REV

The command that was run is

verilator --x-assign fast --x-initial fast -O3 \ -CFLAGS "" \ -Wno-style -Wno-lint -Wno-BLKLOOPINIT -Wno-STMTDLY -Wno-UNOPTFLAT \ -Mdir ./Verilator_obj \ --cc -y src -y tb_v Top.v --exe ./tb_c/main.cpp && \ make -j -C ./Verilator_obj -f VmkTop.mk && \ ./Verilator_obj/VmkTop

Please could you let us know a way to resolve this.

History

#1 Updated by Wilson Snyder 4 months ago

  • Description updated (diff)
  • Status changed from New to AskedReporter

Please attach a complete standalone example so I can try it, thanks. Ideally this would be in test_regress format as described in the documentation, but a tar/zip file that runs standalone could work.

#2 Updated by Wilson Snyder 12 days ago

  • Status changed from AskedReporter to NotEnoughInfo

Thanks for filing this, feel free to reopen if a complete test case can be provided.

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