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Issue #1473

How to get no `line pragmas in preprocessor

Added by Aliaksei Chapyzhenka about 2 months ago. Updated about 2 months ago.

Status:
NoFixNeeded
Priority:
Normal
Assignee:
-
Category:
-
% Done:

0%


Description

As I understand, Verilator preprocessor inserts `line pragmas instead of `include and other directives. It can appear in any place of the Verilog code and it makes Verilog parser job harder. Example: https://github.com/tree-sitter/tree-sitter-verilog/issues/18 Could we have a preprocessor option to disable `line insertion?

History

#1 Updated by Wilson Snyder about 2 months ago

  • Subject changed from no `line pragmas after preprocessor to How to get no `line pragmas in preprocessor
  • Status changed from New to NoFixNeeded

Please see the -P option in the manual.

If you're writing a parser, you might want to consider handling `line for your error tracking, otherwise it will be difficult for your users to know where to fix their code.

#2 Updated by Aliaksei Chapyzhenka about 2 months ago

Wilson Snyder wrote:

Please see the -P option in the manual.

If you're writing a parser, you might want to consider handling `line for your error tracking, otherwise it will be difficult for your users to know where to fix their code.

Great. Thank you.

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