You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
As I understand, Verilator preprocessor inserts line pragmas instead of include and other directives.
It can appear in any place of the Verilog code and it makes Verilog parser job harder.
Example: tree-sitter/tree-sitter-verilog#18
Could we have a preprocessor option to disable `line insertion?
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-26T22:42:28Z
Please see the -P option in the manual.
If you're writing a parser, you might want to consider handling `line for your error tracking, otherwise it will be difficult for your users to know where to fix their code.
Original Redmine Comment
Author Name: Aliaksei Chapyzhenka
Original Date: 2019-06-26T23:57:50Z
Wilson Snyder wrote:
Please see the -P option in the manual.
If you're writing a parser, you might want to consider handling `line for your error tracking, otherwise it will be difficult for your users to know where to fix their code.
Author Name: Aliaksei Chapyzhenka
Original Redmine Issue: 1473 from https://www.veripool.org
As I understand, Verilator preprocessor inserts
line pragmas instead of
include and other directives.It can appear in any place of the Verilog code and it makes Verilog parser job harder.
Example: tree-sitter/tree-sitter-verilog#18
Could we have a preprocessor option to disable `line insertion?
The text was updated successfully, but these errors were encountered: