Document parse-order-dependency for config files
When including a *.vlt configuration file with lint waivers, only the global waivers (file == "*") are applied unconditionally; all file/line-specific waivers are only applied to files parsed after the configuration file has been parsed.
This behavior is not documented so far (and took me some time to figure out), so add a small note in the documentation.
Please find a patch here: https://github.com/imphil/verilator/commit/f937318e14a454ce644645c368b415ae3ea280ec.patch
I'm not sure if you prefer to get pull requests on GitHub now, let me know and I'll do one over there.
#1 Updated by Wilson Snyder 3 months ago
Sorry you had to experiment to figure this out (I didn't realize myself ;) but major thanks for improving the docs.
Trivial really for a doc patch, but so you're set for the future, to the patch please insert your name in docs/CONTRIBUTORS to acknowledge this and future contributions are made under the Developer Certificate of Origin (https://developercertificate.org/). (Needed just once.)
#2 Updated by Philipp Wagner 3 months ago
Sorry for the slow response, looks like the email notification didn't reach me.
An updated patch with a DCO Signed-off-by line is available here: https://github.com/imphil/verilator/commit/836acde22b59685a17a945d37346419ee3996523.patch
And a patch adding my name to the contributors list is here: https://github.com/imphil/verilator/commit/4558efc7151bebabfd37f69b62d0764b3450ee6a.patch
(Both patches are also in my note-config-parse-order branch at https://github.com/imphil/verilator.git
#4 Updated by Shareef Jalloq 2 months ago
I've hit what I think is the same issue today but can't get the waivers to apply. I'm supplying the .wlt configuration file before any Verilog files or paths. I'm using v4.016 and compiled from source. My commandline follows. Is this not the way to fix the issue?
lint: verilator --lint-only -Wall \ $(MODULE).vlt \ -y $(PROJ_HOME)/src/misc/verilog \ -y $(PROJ_HOME)/src/regfile/verilog \ -y $(PROJ_HOME)/src/spis/verilog \ -y $(PROJ_HOME)/src/top/verilog \ $(MODULE).v > $(MODULE).log 2>&1
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