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V3Hashed.cpp Called isIdentical on non-hashed nodes, from Gate dedupe() #1475
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Original Redmine Comment This is with 4.016 as well as 4.014: $ verilator --version |
Original Redmine Comment There was recently a similar error resulting from parameters, are there parameters in DressRehersalTestBench.v? What is near DressRehersalTestBench.v line 18956? If reduction of code makes the bug go away, try the -Oi flag to disable inlining. (It might be the smaller code then gets inlined, hiding the bug.) Try using --debug. Let us know maybe the last 10 lines of the output. |
Original Redmine Comment
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Original Redmine Comment The parameterization happens in Chisel, so Chisel spits out unparameterized files, so the only parameterization I have is in a blackbox inferred RAM Verilog file. It's nowhere near the failure location. |
Original Redmine Comment This is the only other file in the design in addition to DressRehearsalTestBench.v |
Original Redmine Comment I was able to run a bisection to find the first failing version of Verilator:
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Original Redmine Comment Bisecting was a good idea, unfortunately that's was a hyper large change, though I wouldn't have expected those edits to result in this error. What does "verilator --debug --gdbbt" give as a backtrace? |
Original Redmine Comment Is it possible to split that commit into a sequence of commits, purely for the purpose of bisecting it further or is it necessarily a single big commit? |
Original Redmine Comment Here's the last lines when running with "--debug --gdbgt":
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Original Redmine Comment The logfile you attached showed no errors. Perhaps you're still in the passing bisect? |
Original Redmine Comment I'm afraid that I'm only seeing the crash without "--debug --gdbgt", I checked. |
Original Redmine Comment I tried with valgrind, the crash was reproducible, but it didn't report anything. |
Original Redmine Comment Presumably it's --debug that is hiding the issue as the code compiles differently. Try --debugi 3. Also edit line 135 of V3Hashed.cpp with attached patch. |
Original Redmine Comment Output w/patch:
Output with "--debugi 3":
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Original Redmine Comment That helps, but not enough to suggest what to fix so still think we need to get to a testcase. Basically, Verilator suspects that leArrayScanChain_io_leArray_enable feeds to some logic that is probably duplicated and can be simplified, and is getting this error trying to prove it. Please look to see if you can make a test case that involves the signal leArrayScanChain_io_leArray_enable (probably feeding to _T_40457). Another method if you haven't tried it is to see it fail, rip out some code and if still fails keep ripping. Backup if it starts passing. |
Original Redmine Comment I've tried to reduce it along the lines you describe and I've failed. I'm skeptical of this apparoch because simply specifying debug output is enough to make the problem go away, which I assume, means that there's some sort of dangling reference or uninitialize data. Also, I've had a great many variations of this dress rehearsal test and it's only the exact version that I have now that gives Verilator constipation. The failing Verilog is 2.2mBytes uncompressed and 37000 lines of code. It's a scaled down version of what I'm building, which is going to be ~500k lines of Verilog. I can investigate the possibility of emailing you the Verilog file privately and then you can use it to debug the problem, if possible extract a test-case once you understand the problem to put into a test-suite and then delete the Verilog afterwards. Would that be a meaningful way forward? |
Original Redmine Comment Got a test case which shows a replacement is going into a flop which itself is then subject to replacement. This is inside the "Gate dedupe() outputs" stage of optimization. I have ugly code which can detect this case and disable further optimizations on the substituted block, but would prefer to commit something that can continue optimization, unfortunately this requires rework of the data structures. As a temp workaround please try commenting the block of code after printing "Gate dedupe() outputs" in V3Gate.cpp. |
Original Redmine Comment Fixed in git towards 4.017. Thanks for the test case & patience. |
Original Redmine Comment Thanks for fixing this. This must have been an obscure edge case, I only ran into it that once. Given the Verilator test-suite size, I would expect new tests to be more and more obscure. I've been running with quite an old version of Verilator for a year or so, and when I was finally prompted to upgrade, this was the only snag. I'm glad it's in the automated test-suite now. |
Original Redmine Comment In 4.018. |
Author Name: Øyvind Harboe
Original Redmine Issue: 1475 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
I'm getting the error below in BOLD when I invoke Verilator. DressRehearsalTestBench.v is generated by Chisel: https://chisel.eecs.berkeley.edu/
I'm not sure how to proceed with this bug-report as I haven't been able to reduce DressRehearsalTestBench.v to the point where I can include it in the bug-report.
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