Conditional event controls ("iff")
Section 126.96.36.199 of IEEE 1800-2017 allows "iff" qualifiers on @ event controls. The example code in 188.8.131.52 is fairly straightforward:
module latch (output logic [31:0] y, input [31:0] a, input enable); always @(a iff enable == 1) y <= a; //latch is in transparent mode endmodule
I'm currently using Verilator only for lint and I get this error on the above code: syntax error, unexpected iff, expecting ')' or ',' or orThe above code seems equivalent to the following which Verilator does support (at least for lint):
module latch (output logic [31:0] y, input [31:0] a, input enable); always @(a) if (enable == 1) y <= a; //latch is in transparent mode endmoduleI also get lint errors when doing something similar in assertions:
assert property (@(posedge clk iff enable) disable iff (reset) (expr));
Can you introduce iff support? Thanks.
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