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Issue #1482

Conditional event controls ("iff")

Added by Paul Donahue about 2 months ago. Updated about 2 months ago.

Status:
Feature
Priority:
Normal
Assignee:
-
Category:
Unsupported
% Done:

0%


Description

Section 9.4.2.3 of IEEE 1800-2017 allows "iff" qualifiers on @ event controls. The example code in 9.4.2.3 is fairly straightforward:
module latch (output logic [31:0] y, input [31:0] a, input enable);
  always @(a iff enable == 1)
    y <= a; //latch is in transparent mode
endmodule

I'm currently using Verilator only for lint and I get this error on the above code: syntax error, unexpected iff, expecting ')' or ',' or or

The above code seems equivalent to the following which Verilator does support (at least for lint):
module latch (output logic [31:0] y, input [31:0] a, input enable);
  always @(a) if (enable == 1)
    y <= a; //latch is in transparent mode
endmodule
I also get lint errors when doing something similar in assertions:
assert property (@(posedge clk iff enable)
                 disable iff (reset)
                 (expr));

Can you introduce iff support? Thanks.

History

#1 Updated by Wilson Snyder about 2 months ago

  • Category set to Unsupported
  • Status changed from New to Feature

The event parsing needs some rewriting to handle this, but is relatively straight forward.

Added a disabled t_iff.v test as a placeholder.

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