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This was tested using the Verilator 4.016 release. When using a parameter that is an array of enumeration values inside an if (or case) condition of a generate block triggers the following errors:
%Error: test.sv:48: Illegal assignment of constant to unpacked array
%Error: test.sv:48: Generate If condition must evaluate to constant
When changing the array to be packed Verilator will throw only warnings; however the generate block does not evaluate the condition correctly. Attached is a test case that demonstrates this. The example simulates correctly with Incisive and synthesizes with Design Compiler. Icarus Verilog and Yosys unfortunately don't support this syntax.
The text was updated successfully, but these errors were encountered:
Author Name: John Martin (@emmicro-us)
Original Redmine Issue: 1484 from https://www.veripool.org
This was tested using the Verilator 4.016 release. When using a parameter that is an array of enumeration values inside an if (or case) condition of a generate block triggers the following errors:
%Error: test.sv:48: Illegal assignment of constant to unpacked array
%Error: test.sv:48: Generate If condition must evaluate to constant
When changing the array to be packed Verilator will throw only warnings; however the generate block does not evaluate the condition correctly. Attached is a test case that demonstrates this. The example simulates correctly with Incisive and synthesizes with Design Compiler. Icarus Verilog and Yosys unfortunately don't support this syntax.
The text was updated successfully, but these errors were encountered: