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Issue #1495

Wrong statement continue alignment.

Added by Enze Chi 20 days ago. Updated 6 days ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
Indents
% Done:

0%


Description

With verilog-mode from master branch (be9b5af)

I have 3 expression as below, after press <ENTER>, I got wrong alignment for the example code as below:

    startc_c         <= (valid && (state == THE_START));
    end_c             <= (valid && (state == THE_END));
    valid_c           <= (valid &&
                (state != IDLE) &&
                (state != SKIP_DATA));

But the expected alignment should be:
    startc_c  <= (valid && (state == THE_START));
    end_c     <= (valid && (state == THE_END));
    valid_c   <= (valid &&
                         (state != IDLE) &&
                         (state != SKIP_DATA));

verilog-bug-report-dump.txt View - variable dump (3.09 KB) Enze Chi, 09/02/2019 12:08 PM

History

#1 Updated by Wilson Snyder 20 days ago

  • Category set to Indents
  • Status changed from New to AskedReporter

I get:

module x;
   initial begin
      startc_c         <= (valid && (state == THE_START));
      end_c            <= (valid && (state == THE_END));
      valid_c          <= (valid &&
                           (state != IDLE) &&
                           (state != SKIP_DATA));

which seems correct. Perhaps you have some variable settings that change behavior? Please send your verilog-submit-bug-report variable dump.

#2 Updated by Enze Chi 19 days ago

Here's the variable dump

#3 Updated by Enze Chi 19 days ago

I just realise that when I call "verilog-indent-buffer", the alignment is as expected. The problem happens when press "ENTER" at the end of last line in the example code. It will align the "<=" and "!=" which it should not.

#4 Updated by Wilson Snyder 6 days ago

  • Status changed from AskedReporter to Confirmed

Doesn't see a obvious fix; if someone would be willing to investigate further and provide a patch it would be appreciated.

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