Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-09-01T15:09:28Z

I get:

module x;
    initial begin
       startc_c         <= (valid && (state == THE_START));
       end_c            <= (valid && (state == THE_END));
       valid_c          <= (valid &&
                            (state != IDLE) &&
                            (state != SKIP_DATA));

which seems correct. Perhaps you have some variable settings that change behavior? Please send your verilog-submit-bug-report variable dump.

Original Redmine Comment
Author Name: Enze Chi
Original Date: 2019-09-02T12:08:47Z

Here's the variable dump

Original Redmine Comment
Author Name: Enze Chi
Original Date: 2019-09-02T12:16:02Z

I just realise that when I call "verilog-indent-buffer", the alignment is as expected. The problem happens when press "ENTER" at the end of last line in the example code. It will align the "<=" and "!=" which it should not.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-09-15T15:40:36Z

Doesn't see a obvious fix; if someone would be willing to investigate further and provide a patch it would be appreciated.