[VerilogAMS]: Unknown Language Specified #1503
Labels
resolution: wontfix
Closed; work won't continue on an issue or pull request
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Rohit Yadav
Original Redmine Issue: 1503 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Hi,
I am new to Verilator. I am interested in simulating several verilogams test cases with Verilator. I ran the following command to a simple vams file but Verilator fails with the following log:
Standard verilog seems to be work fine but not vams.
I apologize if this has been answered before. I tried searching through the issues history but could not find any related to this.
Regards,
Rohit
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