Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issue #1505

[Bug] cannot understand multi-dimensional array interfaces

Added by Ânderson Ignacio Da Silva 9 days ago. Updated 9 days ago.

Status:
WillNotFix
Priority:
Normal
Assignee:
Category:
Parser
% Done:

0%


Description

Verilator 4.018 cannot parse understand multi-dimensional array using interfaces structures from system verilog. The instantiation below cannot be parsed and raises syntax error of unexpected '['.

https://github.com/pulp-platform/apu_cluster/blob/master/sourcecode/apu_cluster.sv#L88

History

#1 Updated by Wilson Snyder 9 days ago

  • Status changed from New to Confirmed

Agreed this is a mistake in translation of the IEEE grammar. Also applies to Verilog-Perl which will get fixed first.

#2 Updated by Wilson Snyder 9 days ago

Verilog-Perl fixed in version 3.468.

#3 Updated by Wilson Snyder 9 days ago

  • Status changed from Confirmed to WillNotFix

Thanks for the report.

I created a test case and this is not supported in the two commercial simulators I could check. Given that this was turning painful for Verilator I think development time is better spent elsewhere, so not supporting for now. Will reconsider if/when all of the major commercial simulators get there.

However, the error message should have been better as this was unintentionally a syntax error, so added an unsupported message towards version 4.020.

You might want to suggest that the pulp project use only a 1D array to make their code more portable.

Also available in: Atom