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Improve error report when erroneously using interface in expression #1525

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veripoolbot opened this issue Sep 25, 2019 · 2 comments
Closed

Improve error report when erroneously using interface in expression #1525

veripoolbot opened this issue Sep 25, 2019 · 2 comments
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@wsnyder
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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Author Name: Bogdan Vukobratovic (@bogdanvuk)
Original Redmine Issue: 1525 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

When an interface ("din" in this example) is erroneously used in an expression like this:

assign dummy = din.data & din;

Verilator reports the following:

%Error: Internal Error: top.sv:15: ../V3Gate.cpp:440: Var didn't get varscoped in V3Scope.cpp
                                  : ... In instance wrap_dut.din__Viftop
    assign dummy = din.data & din;
                              ^~~
                         ... See the manual and http://www.veripool.org/verilator for more assistance.

Maybe a more informative error can be returned.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-09-26T01:54:08Z

Thanks for your issue. I was unable to get the exact error message you did, but got other ugly messages when misusing an interface, so please check this also fixes your case.

Fixed in git towards eventual 4.020 release.

Here's what it does now:

 %Error: t/t_interface_asvar_bad.v:29: Operator ADD expected non-interface on RHS but 'itf' is an interface.
                                     : ... In instance t.source
       getter = 4'd3 + itf;
                       ^~~

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-06T14:07:52Z

In 4.020. Thanks for reporting this; if there are additional related problems, please open a new issue.

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed labels Dec 22, 2019
@wsnyder wsnyder mentioned this issue May 3, 2020
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed
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