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Issue #1526

SystemVerilog cast on input ports causes signal to be ignored

Added by Udi Finkelstein 4 months ago. Updated about 1 month ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Autos
% Done:

0%


Description

In the following minimal code example, "x" is promoted to output although it's used as both input and output.

Commenting line 22 and uncommenting line 21 solves this issue, showing that the SV casting is the issue.

module t;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output            x;            // From t2 of t2.v
// End of automatics
/*AUTOWIRE*/
wire [3:0][27:0]x;
typedef wire [3:0][27:0]t;
/*t2  AUTO_TEMPLATE  (
  .x(x),
  //.x(t'(x)),
)*/
t2 #(// Parameters
.N(4)
)
t2 (/*AUTOINST*/
    // Outputs
    .x                    (x));             // Templated
/*t3  AUTO_TEMPLATE  (
  //.x(x),
  .x(t'(x)),
)*/
t3 #(// Parameters
.N(4)
)
t3 (/*AUTOINST*/
    // Inputs
    .x                    (t'(x)));         // Templated
endmodule

module t2 #(
parameter N=4
) (
  output [N-1:0][27:0]x
);
endmodule

module t3 #(
parameter N=4
) (
  input [N-1:0][27:0]x
);
endmodule

I'm well aware of the fact that in this example "x" is even generated without dimensions, but at the moment this bothers me less because I declare the wire by myself. The real code where I ran into this uses partial indexing of a multidimensional reg, and I understand from past issues that this isn't supported anyhow.

All I want is just to stop it from being generated by AUTOOUTPUT. I know there are workarounds for disabling ports (dead `ifdefs etc.) but I don't want to add this unnecessarily to the code when it's Verilog-mode's fault.

Also, if I change line 21 to ".x(x[][])," the port is declared as
output [N-1:0] [27:0]    x;            // From t2 of t2.v
Instead of using the assigned parameter value (4).

History

#1 Updated by Wilson Snyder 4 months ago

  • Category set to Autos
  • Status changed from New to Resolved
  • Assignee set to Wilson Snyder

Thanks for the good test case.

Believe I've fixed it, see git and verilog-mode-2019-09-26-ef55eb6-vpo, please give it a try on your larger design.

#2 Updated by Udi Finkelstein 4 months ago

Thanks!

That solved the issue on hand (on my full code), but it caused a new bug :-(

module t;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output            x;            // From t2 of t2.v
// End of automatics
/*AUTOWIRE*/
wire [3:0][27:0]x;
/*t2  AUTO_TEMPLATE  (
  .x((x)),
)*/
t2 #(// Parameters
.N(4)
)
t2 (/*AUTOINST*/
    // Outputs
    .x                    ((x)));             // Templated

wire [27:0]a;
assign a = x[0][27:0];
wire [27:0]b;
assign b = x[1][27:0];

endmodule

module t2 #(
parameter N=4
) (
  output [N-1:0][27:0]x
);
endmodule

Using the previous (Sep 5) version, x is correctly detected and not inferred as output.

Using the new Sep 26 version, x is not detected correctly and inferred as output (as quoted above).

Even for the Sep 5 version, I had to put an extra parenthesis in the template to get it to work, otherwise 'x' would turn into an output as well.

#3 Updated by Wilson Snyder 4 months ago

In your example as I understand it, "x" is an output, and is not used as an input (always's are ignored) and so should correctly be in the autooutput list. It looks like you were relying on a bug in the older version. If you don't want x in the output list you might want to use verilog-auto-ignore-concat.

#4 Updated by Udi Finkelstein 4 months ago

Are you implying that referencing a signal within your module is not enough to keep it internal? Does it has to be an explicit input of another module?

I went over the available documentation, and it seems this is not clearly described. I've been using a different internal tool from my previous workplace in the past, where merely using a signal value within the module is enough to preclude it from the module's outputs, and so this seemd natural to me.

#5 Updated by Wilson Snyder 4 months ago

Are you implying that referencing a signal within your module is not enough to keep it internal?

Correct. Autooutput was originally for modules which just had submodules and it's too late to change the convention.

Verilog-mode-Help

"Make output statements for any output signal from an /*AUTOINST*/ that isn't an input to another AUTOINST.

#6 Updated by Wilson Snyder about 1 month ago

  • Status changed from Resolved to Closed

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