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Running "verilator_bin --cc 3.v" with the attaced testcase does not terminate in a reasonable amount of time. It does produce the output:
%Error: 3.v:1: Too many digits for 32 bit number: 111111111111
... As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)
... Suggest adding a size to it.
111111111111 1111111'd1111111111111111111111111'd
^~~~~~~~~~~~
%Error: 3.v:1: syntax error, unexpected INTEGER NUMBER
111111111111 1111111'd1111111111111111111111111'd
^~~~~~~~~~~~
This is running with:
Verilator 4.019 devel rev v4.018-33-gcb115e1a
The problem is also seen on:
Verilator 3.916 2017-11-25 rev verilator_3_914-65-g0478dbd
In both cases, this is running on Ubuntu 18.04 on x86_64.
The text was updated successfully, but these errors were encountered:
Author Name: Eric Rippey
Original Redmine Issue: 1531 from https://www.veripool.org
Running "verilator_bin --cc 3.v" with the attaced testcase does not terminate in a reasonable amount of time. It does produce the output:
This is running with:
Verilator 4.019 devel rev v4.018-33-gcb115e1a
The problem is also seen on:
Verilator 3.916 2017-11-25 rev verilator_3_914-65-g0478dbd
In both cases, this is running on Ubuntu 18.04 on x86_64.
The text was updated successfully, but these errors were encountered: