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There is a problem when Handling variables forced type conversion #1554
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Original Redmine Comment See the WIDTH section of the manual. I'd provide some examples from other simulators but EDA Playground seems to be having some issues right now. Also, see 11.8.1 of the LRM. Specifically:
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Original Redmine Comment we also use CARBON's CMS tool,the result in line with expectations, it can correctly do type conversion with width variation, Maybe you can learn from its implementation. |
Original Redmine Comment Can you submit a self-checking test, ideally in the test_regress format (see the manual), and ideally passing against VCS or NC-Verilog, as they are generally closer to IEEE compliant. Thanks. |
Original Redmine Comment this is the test code,maybe you can use fore reference. |
Original Redmine Comment Please give a ASCII file which is a few lines long which prints e.g. pass or fail. And runs standalone. |
Original Redmine Comment Waiting on standalone test case. |
Author Name: w z
Original Redmine Issue: 1554 from https://www.veripool.org
Original Assignee: Todd Strader (@toddstrader)
The result of this shift should be related to the bit width of the operation. For example, the previous operation value is only 1 bit, and only 1 bit after shifting, taking a value lower than 1 bit.
Need to specify the variable bit width according to the conversion bit width.
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