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Issue #1554

There is a problem when Handling variables forced type conversion

Added by w z about 1 month ago. Updated 15 days ago.

Status:
AskedReporter
Priority:
Normal
Assignee:
Category:
TranslationError
% Done:

0%


Description

The result of this shift should be related to the bit width of the operation. For example, the previous operation value is only 1 bit, and only 1 bit after shifting, taking a value lower than 1 bit. Need to specify the variable bit width according to the conversion bit width.

v2c type conversion problem.png View (20.3 KB) w z, 10/15/2019 08:35 AM

v2c type conversion test.png View (60.3 KB) w z, 10/16/2019 01:37 AM

History

#1 Updated by Todd Strader about 1 month ago

See the WIDTH section of the manual. I'd provide some examples from other simulators but EDA Playground seems to be having some issues right now. Also, see 11.8.1 of the LRM. Specifically:
The sign and size of any self-determined operand are determined by the operand itself and independent of the remainder of the expression.

#2 Updated by w z about 1 month ago

we also use CARBON's CMS tool,the result in line with expectations, it can correctly do type conversion with width variation, Maybe you can learn from its implementation.

#3 Updated by Wilson Snyder about 1 month ago

Can you submit a self-checking test, ideally in the test_regress format (see the manual), and ideally passing against VCS or NC-Verilog, as they are generally closer to IEEE compliant. Thanks.

#4 Updated by w z about 1 month ago

this is the test code´╝îmaybe you can use fore reference.

#5 Updated by Wilson Snyder about 1 month ago

Please give a ASCII file which is a few lines long which prints e.g. pass or fail. And runs standalone.

#6 Updated by Wilson Snyder 15 days ago

  • Status changed from New to AskedReporter

Waiting on standalone test case.

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