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Author Name: w z Original Redmine Issue: 1555 from https://www.veripool.org
Original Assignee: Todd Strader (@toddstrader)
hi, On RTL, asynchronous reset does not require a falling edge to trigger the initial value.verilaror is inconsistent with rtl.please check.
The text was updated successfully, but these errors were encountered:
Original Redmine Comment Author Name: Todd Strader (@toddstrader) Original Date: 2019-10-15T11:00:39Z
See --x-initial-edge. I think that may resolve your problem.
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Original Redmine Comment Author Name: w z Original Date: 2019-10-16T01:05:14Z
great,thanks very much for your help
toddstrader
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Author Name: w z
Original Redmine Issue: 1555 from https://www.veripool.org
Original Assignee: Todd Strader (@toddstrader)
hi,
On RTL, asynchronous reset does not require a falling edge to trigger the initial value.verilaror is inconsistent with rtl.please check.
The text was updated successfully, but these errors were encountered: