Id: 	30180
Status: 	resolved
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	Nobody
Requestors: 	dbsingh1880 <devendra.singh@>

Severity: 	Important
X Attachments
upcnt4.v

     * Tue Oct 23 14:43:13 2007 (2k) by dbsingh1880

i2c_control.v

     * Tue Oct 23 14:43:14 2007 (33.9k) by dbsingh1880

i2c_blk_ver.v

     * Tue Oct 23 14:43:15 2007 (5.3k) by dbsingh1880

SHIFT8.v

     * Tue Oct 23 14:43:15 2007 (2.3k) by dbsingh1880

uC_interface.v

     * Tue Oct 23 14:43:13 2007 (14.5k) by dbsingh1880

vp15.pl

     * Tue Oct 23 14:43:15 2007 (1.8k) by dbsingh1880

The read_file subroutine generates error when parameters are defined
with module declaration as shown in the example below:

module #(parameter a = 1'b0,
parameter b = 2'b00)
(input reset,
input clk,
output otr);
......
....
endmodule

Also when list of nets is generated for a particular module, it also
contains the parameters.

You're missing the module name. When I add it, and use the latest
version I get what I think is correct, if not please send me the output
you get and how you got it. Also, it's correct that parameters are
listed under nets, it would be better if they were labeled
"identifiers". I'll document that.

module test
#(parameter a = 1'b0,
parameter b = 2'b00)
(input reset,
input clk,
output otr);
endmodule

+ verilog/parser_bugs.v:203: MODULE 'module' 'v2kparam' undef '0'
+ verilog/parser_bugs.v:204: SIGNAL_DECL 'parameter' 'a' '' '' '' '1'b0'
+ verilog/parser_bugs.v:205: SIGNAL_DECL 'parameter' 'b' '' '' '' '2'b00'
+ verilog/parser_bugs.v:206: SIGNAL_DECL 'input' 'reset' '' '' '' ''
+ verilog/parser_bugs.v:206: PORT 'reset'
+ verilog/parser_bugs.v:207: SIGNAL_DECL 'input' 'clk' '' '' '' ''
+ verilog/parser_bugs.v:207: PORT 'clk'
+ verilog/parser_bugs.v:208: SIGNAL_DECL 'output' 'otr' '' '' '' ''
+ verilog/parser_bugs.v:208: PORT 'otr'
+ verilog/parser_bugs.v:203: ENDMODULE 'endmodule'

Subject: 	parameter parse error
From: 	devendra.singh@

Please download all the files attached in a directory and run vp15.pl

This will generate following error
#########################################
%Error: i2c_blk_ver.v:2: syntax error, unexpected parameter, expecting
IDENTIFIER
Exiting due to errors
#########################################

If you remove the parameter declaration, it goes through well.

But there is one more query if you see the generated log,
nets connected to array ports(width>1) does not contain
array attribute value.

[application/octet-stream 14.5k]
Message body not shown because it is too large or is not plain text.

[application/octet-stream 2k]
Message body not shown because it is too large or is not plain text.

[application/octet-stream 33.9k]
Message body not shown because it is too large or is not plain text.

[application/octet-stream 1.8k]
Message body not shown because it is too large or is not plain text.

[application/octet-stream 5.3k]
Message body not shown because it is too large or is not plain text.

[application/octet-stream 2.3k]
Message body not shown because it is too large or is not plain text.

Subject: 	Attached case works in recent versions of Verilog-Mode

Long ago resolved.