Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Memory definition triggers the error "Signal unoptimizable: Feedback to clock or circular logic" #1571

Closed
veripoolbot opened this issue Oct 20, 2019 · 2 comments
Labels
resolution: no fix needed Closed; no fix required (not a bug)

Comments

@veripoolbot
Copy link
Contributor


Author Name: Yuri Z
Original Redmine Issue: 1571 from https://www.veripool.org


I have this statement defining the memory that triggers this error:

reg [7:0] Mem [63:0];

I took it from this line: https://github.com/cpldcpu/MCPU/blob/master/verilog/tb.v#L53

What is wrong? This is essentially a set of wires, why is it unoptimizable?

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Yuri Z
Original Date: 2019-10-20T18:37:40Z


Here they declare the memory in essentially the same way: http://www.asic-world.com/verilog/memory_fsm1.html

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-20T18:52:20Z


The problem isn't that line per-se, but rather the places where it's used. In the case you provided this is a behavioral test (with #delays) that are not supported by verilator, so it's ignoring those. Try it with a design that is synthesizable.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
resolution: no fix needed Closed; no fix required (not a bug)
Projects
None yet
Development

No branches or pull requests

1 participant