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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-20T18:52:20Z
The problem isn't that line per-se, but rather the places where it's used. In the case you provided this is a behavioral test (with #delays) that are not supported by verilator, so it's ignoring those. Try it with a design that is synthesizable.
Author Name: Yuri Z
Original Redmine Issue: 1571 from https://www.veripool.org
I have this statement defining the memory that triggers this error:
I took it from this line: https://github.com/cpldcpu/MCPU/blob/master/verilog/tb.v#L53
What is wrong? This is essentially a set of wires, why is it unoptimizable?
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