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Issue #1594

Add interface port visibility in traces

Added by Todd Strader 11 days ago. Updated 9 days ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
-
% Done:

0%


Description

See: https://github.com/toddstrader/verilator-dev/tree/iface-vcd

Users should not have to know where an interface was instantiated to pull it up in the trace. This adds the interface "module" everywhere there is an interface port. I extended t_interface1_modport_trace to check the VCD and added t_interface1_modport_trace_fst for the FST.

Please let me know what you think. I'm ready to squash and push this one once reviewed.


Related issues

Related to Issue #1595: Fix interface reference tracing Assigned

History

#1 Updated by Wilson Snyder 11 days ago

  • Status changed from New to Assigned

Good idea.

Only nit is to put braces around the iteration and reorder a bit to clarify how you are save/restoring the variables. e.g.

// Stash the signal state because we're going to go through another VARSCOPE
AstVarScope* traVscp = m_traVscp;
AstNode* traValuep = m_traValuep;
{
    m_traVscp = NULL;
    m_traValuep = NULL;
    m_ifShowname = m_traShowname;
    m_traShowname = "";
    iterate(nodep->ifacep());
    m_traShowname = m_ifShowname;
    m_ifShowname = "";
}
m_traVscp = traVscp;
m_traValuep = traValuep;

Then feel free to squash push.

#2 Updated by Todd Strader 11 days ago

  • Status changed from Assigned to Resolved

Done.

#3 Updated by Wilson Snyder 9 days ago

  • Status changed from Resolved to Closed

In 4.022.

#4 Updated by Todd Strader 8 days ago

  • Related to Issue #1595: Fix interface reference tracing added

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