// This code compiles on Verilator 3.9xx; but 4.0xx fails with the error:
// %Error: Internal Error: top.v:32: ../V3Split.cpp:658: Unknown node in split color() map

`define COND (2'b10)

module top (
     input  wire clk,
     input  wire aresetn
);

     reg [9:0] ten;
     reg [1:0] two;

     function [1:0] func(
         input [1:0]  p0_x,
         input [1:0]  p0_y,
         input [1:0]  p1_x,
         input [1:0]  p1_y,
         input [1:0]  sel);

         reg [1:0] rx;
         reg [1:0] ry;

     begin

`ifdef NOT_DEF
         // This way works
         rx = sel == `COND ? p1_x : p0_x;
         ry = sel == `COND ? p1_y : p0_y;
`else
         // This way fails to compile
         if (sel == `COND)
         begin
           rx = p1_x;
           ry = p1_y;
         end else
         begin
           rx = p0_x;
           ry = p0_y;
         end
`endif
         func = 0;
     end
     endfunction

     always @(*) begin
         two = func(
                     ten[8 +: 2],
                     ten[6 +: 2],
                     ten[4 +: 2],
                     ten[2 +: 2],
                     ten[0 +: 2]);
     end

endmodule