module top (
  input  wire       clk,
  input  wire       rst_n,
  output reg  [1:0] out);
  
  reg [1:0] one, nil;
  
  localparam CORES=1;
  
  always @(posedge clk or negedge rst_n) begin
     integer i;
     if (!rst_n) begin
       out <= 2'b0;
       nil <= 2'b0;
       one <= 2'b0;
     end else begin   
       for (i=0; i<CORES-1; i=i+1) begin // should always set i=0
         nil[i] <= 1'b1; // never happens
       end
       // i should always be 0 here; but is 0 only in the first cycle after reset, then 1
       out[i] <= 1'b1;
       for (i=0; i<CORES; i=i+1) begin
         one[i] <= 1'b1;
       end
     end
  end
  
endmodule