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Interface parameter circular assignment succeeds where it should not #1626

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veripoolbot opened this issue Dec 6, 2019 · 2 comments
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area: data-types Issue involves data-types area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve

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Author Name: Driss Hafdi
Original Redmine Issue: 1626 from https://www.veripool.org


Verilator seems to allow a circular parameter assignment between two interfaces defined in the same scope. This diff (drissos@c8f24e9) includes a small testbench that can reliably reproduce this issue.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-06T22:46:36Z


Thanks for the test. This might be a consequence of how elaboration mis-works (#�), but will take a look.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-07T18:49:56Z


Pushed the test_regress/t/t_itnerface_param_loop_bad.v test with an unsupported() tag (so doesn't run).

@veripoolbot veripoolbot added area: data-types Issue involves data-types area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve labels Dec 22, 2019
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Labels
area: data-types Issue involves data-types area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve
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