Interface parameter circular assignment succeeds where it should not #1626
Labels
area: data-types
Issue involves data-types
area: lint
Issue involves SystemVerilog lint checking
effort: days
Expect this issue to require roughly days of invested effort to resolve
Author Name: Driss Hafdi
Original Redmine Issue: 1626 from https://www.veripool.org
Verilator seems to allow a circular parameter assignment between two interfaces defined in the same scope. This diff (drissos@c8f24e9) includes a small testbench that can reliably reproduce this issue.
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