counter.v :
####################################################################################################
module counter (clk,rst,clear,set_ff,load,up,data,q,test_sig);
input  clk    ;
input  rst    ;
input  clear  ;
input  set_ff ;
input  load   ;
input  up     ;
input  [7:0] data  ;
output [7:0] q     ;
output test_sig;
reg    [7:0] internal_storage;
wire   tst1/*verilator public*/;
wire   tst2/*verilator public*/;
wire   tst3;

always @(posedge clk)
         begin
           	if (rst) begin
             		internal_storage <= 8'h00;
                 end else if (clear) begin
                         internal_storage <= 8'h00;
                 end else if (set_ff) begin
                         internal_storage <= 8'hFF;
                 end else begin
                         if (load) begin
                                 internal_storage <= data;
                         end else begin
                                 if (up) begin
                                         internal_storage <= internal_storage + 1'b1;
                                 end else begin
                                         internal_storage <= internal_storage - 1'b1;
                                 end

                         end
                 end
         end

assign q = internal_storage;

driver driver1 (clk,tst1,tst2);

assign tst3 = tst1 & tst2;
assign test_sig = tst3;

endmodule

module driver (clk,test1,test2);
input clk;
output test1,test2;
reg reg1,reg2;

always @(posedge clk) begin
reg1 <= 1'b1;
reg2 <= 1'b1;
end

assign test1 = reg1;
assign test2 = reg2;

endmodule

####################################################################################################
tb_counter.cpp

#include <stdlib.h>
#include "Vcounter.h" 
#include "Vcounter_counter.h" 
#include "verilated_vcd_c.h"
#include "verilated.h"

int main (int argc, char **argv){

	int i;

	//Initialize Verilator variables
	Verilated::commandArgs(argc,argv);
	//Create a instance of our module under test
	Vcounter *top = new Vcounter;
	//Init trace dump
	Verilated::traceEverOn(true);
	VerilatedVcdC* tfp = new VerilatedVcdC;
	top->trace (tfp, 99);
	tfp->open("counter_top.vcd");

	top->clk = 0;
     	top->rst = 0;
     	top->clear = 0;
     	top->set_ff = 0;
     	top->load = 0;
     	top->up = 1;
     	top->data = 0x00;	
	top->counter->tst1 = 1;
	top->counter->tst2 = 1;

	//top->clk = ! top->clk;
	//top->eval();

	
	for(i=0;i<100;i++){

		top->rst = (i < 2);
		tfp->dump(i);
		if (i<50)top->up = 1; else top->up=0; 
		if (i == 56) top->clear = 1;
		if (i == 57) top->clear = 0;
		if (i == 58) top->set_ff = 1;  
		if (i == 59) top->set_ff = 0;  
		if (i == 66) {top->load = 1; top->data = 0xAA;}
		if (i == 67) top->load = 0; 
		if (i == 12) {
			top->counter->tst1 = 0;
			top->counter->tst2 = 0;}
		if (i == 13) {
			top->counter->tst1 = 0;
			top->counter->tst2 = 0;}
		if (i == 14) {
			top->counter->tst1 = 0;
			top->counter->tst2 = 0;}
		if (i == 16) {
			top->counter->tst1 = 0;
			top->counter->tst2 = 0;}
		if (i == 17) {
			top->counter->tst1 = 0;
			top->counter->tst2 = 0;}
		if (i == 18) {
			top->counter->tst1 = 0;
			top->counter->tst2 = 0;}
		if (i == 21) {
			top->counter->tst1 = 0;
			top->counter->tst2 = 0;}
		if (i == 25) {
			top->counter->tst1 = 0;
			top->counter->tst2 = 0;}
		top->clk = ! top->clk;
		top->eval();

	if(Verilated::gotFinish()) exit (EXIT_SUCCESS);
	}

	tfp->close();
	exit(EXIT_SUCCESS);

}

####################################################################################################