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Author Name: Devendra Singh
Original Redmine Issue: 165 from https://www.veripool.org
Original Date: 2009-02-08
Original Assignee: Wilson Snyder (@wsnyder)
This bug was cloned from Perl-RT, rt43116.
Email addresses have have been truncated.
Id: 43116
Status: resolved
Left: 0 min
Queue: Verilog-Perl
Owner: Nobody
Requestors: dbsingh1880 <devendra.singh@>
Severity: Critical
Broken in: 3.110
X Attachments
temp_pkg.sv
* Sun Feb 08 01:40:03 2009 (289b) by dbsingh1880
temp_mod.sv
* Sun Feb 08 01:40:03 2009 (1k) by dbsingh1880
Sun Feb 08 01:40:03 2009 dbsingh1880 - Ticket created
Subject: typedef parse error for system verilog
Hi,
It was trying to parse system verilog files attached with vhier, but
get the following error.
Probably the parser is not able to get the typedef's from the package
file.
I will appreciate if this can be resolved as I wish to use this in my
script.
vhier temp_mod.sv
%Error: temp_mod.sv:8: syntax error, unexpected "IDENTIFIER", expecting
')'
%Error: temp_mod.sv:20: syntax error, unexpected "output", expecting
"IDENTIFIER"
%Error: temp_mod.sv:29: syntax error, unexpected ')', expecting ',' or
';'
Exiting due to errors
Subject: temp_pkg.sv
package temp_pkg;
typedef enum logic {FALSE, TRUE} false_true;
typedef logic@two_bits;
typedef logic@three_bits;
typedef logic@nibble;
typedef logic@five_bits;
typedef logic@six_bits;
typedef logic@seven_bits;
typedef logic@byte_wide;
endpackage
Subject: temp_mod.sv
module temp_mod
(
//Inputs
input sys_lclk,
input sys_lrst,
input scram_enable,
input gen_speed,
input two_bits rx_invalid,
input two_bits rx_par,
input rxStart_in,
input two_bits Char_in,
input Valid_in,
input word_wide rx_data,
input [22:0] init_seed,
input last_eieos_bit,
input last_fts_bit,
//Outputs
output logic [22:0] flsr,
output scr_invalid0, scr_invalid1,
output scr_par0, scr_par1,
output word_wide aligndata,
output two_bits rxSyncChar,
output rxStart,
output rxValid,
output logic didle_det0, didle_det1
);
import temp_pkg::byte_wide;
import temp_pkg::nibble;
import temp_pkg::two_bits;
import temp_pkg::word_wide;
import temp_pkg::false_true;
import temp_pkg::FALSE;
import temp_pkg::TRUE;
endmodule
Sun Feb 08 07:25:25 2009 WSNYDER - Correspondence added
I am working on this support along with some other SystemVerilog
features, but it will probably be a few weeks, as typedefs are very
complicated.
Sun Feb 08 07:25:27 2009 RT_System - Status changed from 'new' to 'open'
This is fixed in the beta candidate in GIT at veripool.org. It will be
in 3.200.
If you have additional issues please use the bug tracker at
veripool.org, thanks.
Tue Apr 07 06:37:28 2009 WSNYDER - Status changed from 'open' to 'resolved'
The text was updated successfully, but these errors were encountered:
Author Name: Devendra Singh
Original Redmine Issue: 165 from https://www.veripool.org
Original Date: 2009-02-08
Original Assignee: Wilson Snyder (@wsnyder)
This bug was cloned from Perl-RT, rt43116.
Email addresses have have been truncated.
Sun Feb 08 01:40:03 2009 dbsingh1880 - Ticket created
Sun Feb 08 07:25:25 2009 WSNYDER - Correspondence added
Sun Feb 08 07:25:27 2009 RT_System - Status changed from 'new' to 'open'
Tue Apr 07 06:37:27 2009 WSNYDER - Correspondence added
Tue Apr 07 06:37:28 2009 WSNYDER - Status changed from 'open' to 'resolved'
The text was updated successfully, but these errors were encountered: