Id: 	43138
Status: 	resolved
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	Nobody
Requestors: 	dbsingh1880 <devendra.singh@>

Severity: 	Important
Broken in: 	3.110

Subject: 	parse error with nested list

if nested assignment (multiple "{{") is used the parser generates
error....
example code with response is provided below

==================example code======================================
module am
(/*autoarg*/);

output a,b,c,d,e,f;
input@z;
wire a,b,c,d,e,f;

assign {{a,b},c,d,e,f} = z;
endmodule // am

=======================response======================================
[root@punelabpc10 /tmp]$ vhier am.v
%Error: am.v:8: syntax error, unexpected '{', expecting "IDENTIFIER"
Exiting due to errors
[root@punelabpc10 /tmp]$

Thanks for the report. I fixed this in the GIT version available from
veripool.org and this will be in the next release.

If there's more issues please use the bug reporter on veripool.org as
it's less work for me, thanks.