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Issue #1661

How is ppdefine in SigParser used

Added by Topa Tota about 1 month ago. Updated about 1 month ago.

Status:
NoFixNeeded
Priority:
Normal
Assignee:
-
% Done:

0%


Description

.. below

History

#1 Updated by Topa Tota about 1 month ago

Sorry Clicked on create and can't edit it. I'll rewrite below:

Whenever I attempt to parse a file using Verilog::SigParser that has preprocessor definitions, I get an error that Define or directive not defined. Is this intended


my $filename = "test.v";
my $parser = Verilog::SigParser->new();
$parser->parse_file($filename);

How do you use ppdefine callback if SigParser will always give an error when a preprocessor definition is present? Is this a bug?

Also, not much related but when I run parse() and eof() with Verilog::SigParser, I get "syntax error, unexpected IDENTIFIER". This doesn't happen with Verilog::Parser. Is it intended?


my $code = "test";
my $parser = Verilog::SigParser->new();
$parser->parse($code);
$parser->eof();

#2 Updated by Wilson Snyder about 1 month ago

  • Description updated (diff)
  • Status changed from New to NoFixNeeded

To use SigParser you need to pass preprocessed data. See "man Verilog::SigParser":

my $pp = Verilog::Preproc->new(keep_comments=>0,);
my $parser = new Verilog::SigParser;
$parser->parse_preproc_file($pp);

Also see the test files.

#3 Updated by Topa Tota about 1 month ago

Wilson Snyder wrote:

To use SigParser you need to pass preprocessed data. See "man Verilog::SigParser":

my $pp = Verilog::Preproc->new(keep_comments=>0,); my $parser = new Verilog::SigParser; $parser->parse_preproc_file($pp);

Also see the test files.

Ok, I looked at test files and couldn't find ppdefine used anywhere. Below is an example. Please let me know if I am misunderstanding anything.


package MyParser;
use Verilog::SigParser;
use parent qw(Verilog::SigParser);

sub new {
    my $class = shift;
    my $self = $class->SUPER::new(@_);
    bless $self, $class;
    return $self;
}

sub ppdefine {
    my $self = shift;
    my $defvar = shift;
    my $definition = shift;
    print "defvar: $defvar \t\t definition: $definition\n\n";
}

# just for testing everything is working
sub module {
    print "module called!\n";
}

package main;
use Verilog::Preproc;

my $filename = "test.sv";
my $pp = Verilog::Preproc->new();
my $parser = MyParser->new();
$pp->open($filename);
$parser->parse_preproc_file($pp);

`define test test2
`define test2 localparam a = 3;
module test();
`test2
endmodule

Based on the documentation,

$self->ppdefine($defvar, $definition)

This method is called when a preprocessor definition is encountered.

I should get 3 callbacks to $self->ppdefine($defvar, $definition). However, I am only getting a callback $self->module().

#4 Updated by Wilson Snyder about 1 month ago

ppdefine/ppinclude are very old remnants of a perl preprocessor. I have just removed them. If you want to see defines, override Verilog::Preproc's define() (or Verilog::Getopt's).

Your example doesn't see mymeta as it didn't add it to the metacomment hash.

my $parser = MyParser->new(metacomment => {'mymeta'=>1});

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