Original Redmine Comment
Author Name: Topa Tota
Original Date: 2020-01-15T05:02:55Z

Sorry Clicked on create and can't edit it. I'll rewrite below:

Whenever I attempt to parse a file using Verilog::SigParser that has preprocessor definitions, I get an error that Define or directive not defined. Is this intended

my $filename = "test.v";
my $parser = Verilog::SigParser->new();
$parser->parse_file($filename);
</code>

How do you use ppdefine callback if SigParser will always give an error when a preprocessor definition is present? Is this a bug?

Also, not much related but when I run parse() and eof() with Verilog::SigParser, I get "syntax error, unexpected IDENTIFIER". This doesn't happen with Verilog::Parser. Is it intended?

my $code = "test";
my $parser = Verilog::SigParser->new();
$parser->parse($code);
$parser->eof();
</code>

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2020-01-15T12:05:34Z

To use SigParser you need to pass preprocessed data. See "man Verilog::SigParser":

my $pp = Verilog::Preproc->new(keep_comments=>0,);
my $parser = new Verilog::SigParser;
$parser->parse_preproc_file($pp);

Also see the test files.

Original Redmine Comment
Author Name: Topa Tota
Original Date: 2020-01-15T16:41:54Z

Wilson Snyder wrote:

To use SigParser you need to pass preprocessed data. See "man Verilog::SigParser":

my $pp = Verilog::Preproc->new(keep_comments=>0,);
my $parser = new Verilog::SigParser;
$parser->parse_preproc_file($pp);

Also see the test files.

Ok, I looked at test files and couldn't find ppdefine used anywhere. Below is an example. Please let me know if I am misunderstanding anything.

package MyParser;
use Verilog::SigParser;
use parent qw(Verilog::SigParser);

sub new {
     my $class = shift;
     my $self = $class->SUPER::new(@_);
     bless $self, $class;
     return $self;
}

sub ppdefine {
     my $self = shift;
     my $defvar = shift;
     my $definition = shift;
     print "defvar: $defvar \t\t definition: $definition\n\n";
}

1. just for testing everything is working
sub module {
     print "module called!\n";
}


package main;
use Verilog::Preproc;

my $filename = "test.sv";
my $pp = Verilog::Preproc->new();
my $parser = MyParser->new();
$pp->open($filename);
$parser->parse_preproc_file($pp);
</code>

`define test test2
`define test2 localparam a = 3;
module test();
`test2
endmodule
</code>

Based on the documentation,

$self->ppdefine($defvar, $definition)

This method is called when a preprocessor definition is encountered.

I should get 3 callbacks to $self->ppdefine($defvar, $definition). However, I am only getting a callback $self->module().

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2020-01-15T23:39:19Z

ppdefine/ppinclude are very old remnants of a perl preprocessor. I have just removed them. If you want to see defines, override Verilog::Preproc's define() (or Verilog::Getopt's).

Your example doesn't see mymeta as it didn't add it to the metacomment hash.

  my $parser = MyParser->new(metacomment => {'mymeta'=>1});