New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Support signal declarations in loop initialisers #172
Comments
Original Redmine Comment This is a great first project as it's mostly the parser. Let me know when/if you'd like to get started. |
Original Redmine Comment Thanks Wilson, I'm planning on starting this one today, we're aiming to get all four features (102, 170-172) supported in the next few weeks. |
Original Redmine Comment Great! I had a bunch of changes staged for 3.800 that I was holding in case there were bugs on 3.700. I could make a branch, but I just pushed them to make patching easier. So be sure to 'git' the latest. So here's how I'd approach this: Make a testcase in the t_EXAMPLE format, attach here for reference. Look at the grammar in the git version of VerilogPerl's src/VParseGrammar.y as this grammar supports what you want. Then copy the appropriate rules to src/verilog.y and modify the productions to match similar variable declaration rules elsewhere in verilog.y. I'd put a AstBegin(unnamed) wrapper over the AstFor, then the variables land under the AstBegin. (You can do that for all For loops even if they don't have variables.) I think this will require minimal changes elsewhere. Now you can run "test_regress/t/t_{new testcase}.pl --debug" and it'll probably fail but you'll see a test_regress/obj_dir/t_{newtestcase}/*.tree file which you can examine to see if the parsing worked. See also the other test_regress/driver.pl debugging flags. Good luck, drop me a note as you have questions. |
Original Redmine Comment Attaching a testcase which has been run in another simulator and a patch to implement the feature in Verilator. |
Original Redmine Comment Patch committed for next release 3.730+. |
Original Redmine Comment In 3.800. |
Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 172 from https://www.veripool.org
Original Date: 2009-11-03
Original Assignee: Byron Bradley (@bbradley)
Support signal declarations in loop initialisers. Testcase will be attached soon.
The text was updated successfully, but these errors were encountered: