Make parentheses around a single module parameter optional #179
Labels
resolution: fixed
Closed; fixed
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 179 from https://www.veripool.org
Original Date: 2009-11-10
Original Assignee: Byron Bradley (@bbradley)
The parentheses around parameters when a module is instantiated is optional in VCS if there is only one parameter, e.g.:
works in VCS but Verilator currently requires #(PAR) and #(10).
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