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Make parentheses around a single module parameter optional #179

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veripoolbot opened this issue Nov 10, 2009 · 3 comments
Closed

Make parentheses around a single module parameter optional #179

veripoolbot opened this issue Nov 10, 2009 · 3 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 179 from https://www.veripool.org
Original Date: 2009-11-10
Original Assignee: Byron Bradley (@bbradley)

The parentheses around parameters when a module is instantiated is optional in VCS if there is only one parameter, e.g.:

      m1 #PAR m1();                                                                                                                
      m3 #PAR m3();                                                                                                                
      mnooverride #10 mno();

works in VCS but Verilator currently requires #(PAR) and #(10).
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Original Redmine Comment
Author Name: Byron Bradley (@bbradley)
Original Date: 2009-11-10T20:55:29Z

Attached diff makes these parentheses optional and includes a testcase. I've also rolled in a typo fix to Changes and made it ignore vim backup files.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-11-10T21:40:24Z

Thanks! I'll forgive your use of VI this time, since I botched your name. :)

Pushed to git for 3.730++.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-02-07T12:41:22Z

In 3.800.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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