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Question: auto not descending into `include files ... #181
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Original Redmine Comment Hmmm, forum formated my post poorly. Attaching files. |
Original Redmine Comment
No, sorry. The way it's assumed you'd do things like this is to use /AUTOINOUTMODULE("xunit.ports.v")/ xunit.ports.v would then need a module/endmodule; they can be ifdef'ed if you wish:
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Original Redmine Comment BTW the other advantage of AUTOINOUTMODULE is then you don't need to maintain two includes; just one will do it and use /AUTOARG/ to autogenerate the port list (or use verilog 2001 syntax). |
Original Redmine Comment Hmm.... Maybe this instead of the include? I'm not sure it will be replaced in time for the autos to work.
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Original Redmine Comment
If it doesn't expand at all you might have a old version. If it doesn't I'm curious, and didn't want you to download with little hope of success, so ran an experiment. It works great. BTW There's no point in using the port file, Verilog-Mode will do it for you:
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Original Redmine Comment
I tried it, and noticed there's a bug that it doesn't clean up what it inserts properly.
It works. Since it's inlined, you need to save the tinc file, auto-expand the child (module with insertlisp) first, then move to the parent. (Just as if you added the input in the non-included place.) |
Author Name: Clay Douglass
Original Redmine Message: 176 from https://www.veripool.org
I am working with some files that have the port list and input/output declaration in included files e.g.
If I verilog-auto in xunit_top.v it does nothing. If I manually replace the include with the file content it works fine. Is there a setting to make it follow the `include when it parse for ports?
Thanks,
Clay
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