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Author Name: ashutosh khare
Original Redmine Issue: 182 from https://www.veripool.org
Original Date: 2009-11-11
Original Assignee: Wilson Snyder (@wsnyder)
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-11-11T12:15:39Z
That's correct, clk_va is a symbol, it's attached to another symbol with the . operator. Symbols are single things you run through a symbol table; for example you don't want clk_va.du_fu to be all one symbol because you couldn't tell the difference between it and
"\clk_va.du_fu ".
KEYWORD 'always_ff'
OPERATOR '@'
OPERATOR '('
KEYWORD 'posedge'
SYMBOL 'clk_va'
OPERATOR ')'
SYMBOL 'du_fu'
OPERATOR '.'
SYMBOL 'opcode'
OPERATOR '<='
SYMBOL 'opcode'
OPERATOR ';'
Author Name: ashutosh khare
Original Redmine Issue: 182 from https://www.veripool.org
Original Date: 2009-11-11
Original Assignee: Wilson Snyder (@wsnyder)
In system verilog
always_ff @(posedge clk_va)
du_fu.opcode <= opcode;
such kind of assignment is posseible.
I guess symbol call back rule does not handle identifier of type "du_fu.opcode"
I am getting du_fu as symbol
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