New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Trace option is not working anymore #198
Comments
Original Redmine Comment What does the declaration of o_Slave8_SEL look like, in Verilog and in the C++ code? Did this used to work? (given the bug title...) |
Original Redmine Comment My mistake. I assumed it has been tested and broken just lately. |
Original Redmine Comment Wilson Snyder wrote:
It is one bit signal: |
Original Redmine Comment Normally a one bit signal would be a bool, that's probably related to the problem. What flags are you using? |
Original Redmine Comment Wilson Snyder wrote:
I think "--pins-bv 1" created this problem. |
Original Redmine Comment Yup, the --pins-bv test didn't have tracing turned on. I added tracing and it failed. BTW using sc_bv<1> is probably 2x slower than using bools in the SystemC code, if you do that everywhere. Fixed in git for next release; patch below because it'll be several weeks at least.
|
Original Redmine Comment In 3.800. |
Author Name: Michael S
Original Redmine Issue: 198 from https://www.veripool.org
Original Date: 2009-12-25
Original Assignee: Wilson Snyder (@wsnyder)
I have verilator-3.720 and SystemPerl-1.332
The text was updated successfully, but these errors were encountered: