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verilog parser error #202

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veripoolbot opened this issue Jan 11, 2010 · 7 comments
Closed

verilog parser error #202

veripoolbot opened this issue Jan 11, 2010 · 7 comments
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Author Name: Rick Ramus
Original Redmine Issue: 202 from https://www.veripool.org
Original Date: 2010-01-11
Original Assignee: Wilson Snyder (@wsnyder)

module top (out,in); 

output [3:0] out;
input [3:0]  in;
node [2:0] int;

`define BUF(out,in)                                                   \
    assign out = in ;                                                  \
`endif

 `BUF(int, in[2:0])
 `BUF(out, {in[3], int})

endmodule

produces the following error:
%Error: <verilog_path>/top.vs:13: Define passed wrong number of arguments: BUF
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-11T21:51:39Z

Ignoring the extra endif and that int is a reserved word, I think this was fixed a week ago when System Verilog 2009 define enhancements were put in. Please try the git version and let me know.

That will be in the next release, another week or so.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-21T21:23:13Z

In 3.230.

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Original Redmine Comment
Author Name: Rick Ramus
Original Date: 2010-01-25T21:32:13Z


`define FC_INV(out, in)                                                   \
`ifdef MACRO_ATTRIBUTE \
  (* macro_attribute = `"FC_INV (out``,in``)`" *) \
`endif \
  assign out = ~in ;

`define FC_INV1(out, in)                                                   \
`ifdef DC                                                                     \
      yg0inn30nn1g7 \fc_inv_``out <$typeof(out)> (.a(<in>), .o(<out>));   \
  `else                                                                         \
    `ifdef MACRO_ATTRIBUTE \
       (* macro_attribute = `"FC_INV (out``,in``)`" *) \
    `endif \
    assign out = ~in ;                                                \
`endif

`define FC_INV2(out, in)                                                   \
`ifdef DC                                                                     \
      yg0inn30nn1g7 \fc_inv_``out <$typeof(out)> (.a(<in>), .o(<out>));   \
       /* comment */ \
  `else                                                                         \
    `ifdef MACRO_ATTRIBUTE \
       (* macro_attribute = `"FC_INV (out``,in``)`" *) \
    `endif \
    assign out = ~in ;                                                \
`endif

`define FC_INV3(out, in)                                                   \
`ifdef DC                                                                     \
      yg0inn30nn1g7 \fc_inv_``out <$typeof(out)> (.a(<in>), .o(<out>));   \
       /* multi-line comment \
          multi-line comment */ \
  `else                                                                         \
    `ifdef MACRO_ATTRIBUTE \
       (* macro_attribute = `"FC_INV (out``,in``)`" *) \
    `endif \
    assign out = ~in ;                                                \
`endif

produces the following error: %Error: <verilog_path>/top.vs:29: Internal Error: VPreproc.cpp:695: Bad define text
Stopped at /Verilog/Parser.pm line 179

I ran with recently released Verilog-Perl version 3.23

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-25T21:51:24Z

Works for me, maybe you're not really getting the version you think?

perl -e 'use Verilog::Language; print $Verilog::Language::VERSION'

Here's what I get

$ ./vppreproc -DMACRO_ATTRIBUTE a.v
...
 (* macro_attribute = "FC_INV (a,b)" *) assign a = ~b ;
 (* macro_attribute = "FC_INV (a1,b1)" *) assign a1 = ~b1 ;
 (* macro_attribute = "FC_INV (a2,b2)" *) assign a2 = ~b2 ;
 (* macro_attribute = "FC_INV (a3,b3)" *) assign a3 = ~b3 ;

$ ./vppreproc -DDC a.v
 assign a = ~b ;
 yg0inn30nn1g7 \fc_inv_a1 <$typeof(a1)> (.a(<b1>), .o(<a1>));
 yg0inn30nn1g7 \fc_inv_a2 <$typeof(a2)> (.a(<b2>), .o(<a2>));
 yg0inn30nn1g7 \fc_inv_a3 <$typeof(a3)> (.a(<b3>), .o(<a3>));

1. The <>'s seem like mistakes in your example.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-27T22:34:29Z

(Offline test case sent)

Thanks for the testcase, now I see that what is needed to expose it the default stripping
of comments. I'll fix it asap as I think it's simple. Meanwhile a simple workaround for the
current release is:

 my $nl = Verilog::Netlist->new (options => $opt, keep_comments=>1);

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-29T00:34:46Z

Fixed in git for next release, 3.231+.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-02-21T12:35:26Z

In 3.231.

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