Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Support multi-dimensional packed arrays of wires #206

Closed
veripoolbot opened this issue Jan 19, 2010 · 1 comment
Closed

Support multi-dimensional packed arrays of wires #206

veripoolbot opened this issue Jan 19, 2010 · 1 comment
Assignees
Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

Comments

@veripoolbot
Copy link
Contributor


Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 206 from https://www.veripool.org
Original Date: 2010-01-19
Original Assignee: Wilson Snyder (@wsnyder)


reg [1:0][1:0][1:0] works but wire [1:0][1:0][1:0] doesn't. A patch is attached to show this in t/t_mem_packed and it has been tested on another simulator.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-25T12:52:45Z


Fixed in git; thanks for the testcase.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
Projects
None yet
Development

No branches or pull requests

2 participants