Support multi-dimensional packed arrays of wires #206
Labels
resolution: fixed
Closed; fixed
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 206 from https://www.veripool.org
Original Date: 2010-01-19
Original Assignee: Wilson Snyder (@wsnyder)
reg [1:0][1:0][1:0] works but wire [1:0][1:0][1:0] doesn't. A patch is attached to show this in t/t_mem_packed and it has been tested on another simulator.
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