Signals in a concatenation on the LHS aren't created implicitly #208
Labels
resolution: fixed
Closed; fixed
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 208 from https://www.veripool.org
Original Date: 2010-01-19
Original Assignee: Byron Bradley (@bbradley)
Signals in a concatenation on the LHS aren't created implicitly, e.g.:
Fails to create dummy1 and dummy2. Test case and proposed patch attached, I originally just checked for VarRefs in op[1234]p but didn't see any harm in calling pinImplicitExprRecurse() instead.
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