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Compiling verilated code with MSVC #209
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Original Redmine Comment The "int" conflicts should only be reported on top level ports, not internal nets. I'm reluctant to rename top ports as people use scripts that assume one-to-one naming, and "int" has been reserved now for 5 years. Other users have used MSVC++, but I think they are using newer versions. Can you try a more recent release, esp for the long identifiers? I'm sure there will still be some issues I'll be happy to fix. |
Original Redmine Comment
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Original Redmine Comment Well "double" is also SystemVerilog reserved, and "for" a Verilog keyword, but anyhow I think I might have been confused as to what you needed. Assuming you are getting the SYMRSVDWORD error message, you can just turn off that error and it should work - it'll rename the ports. For the compiler issues, please checkout the git version (as there's lots of changes since the last release - a major release is coming in a week) and report what needs changing, or even better attempt fixing them and attach the "git diff origin/master" output. Since recent MSVC versions work OK, I unfortunately don't have the time to fix the long identifiers, especially as it'll break some warning messages (verilator assumes you can map the long symbol back to the original name). However if you'd like to make a fix for your project, I'll take the patch back. V3Name is the place to do it; make a map<> to rename signal over a specified length to something short. Then add code to V3Options around line 778 when given "--compiler msvc-2003" to set that maximum length to whatever crazy limits the MSVC people came up with. If you need more help let me know. |
Original Redmine Comment Ok, Thanks. |
Original Redmine Comment The git versions of SystemPerl and Verilator output now contain your fixes plus some to compile on MSVC++ 2008. If you have patches you want for an earlier version send them along. |
Original Redmine Comment In 3.800. |
Author Name: Amir Gonnen
Original Redmine Issue: 209 from https://www.veripool.org
Original Date: 2010-01-20
Original Assignee: Wilson Snyder (@wsnyder)
verilator-3.720, Visual Studio 2003.
Compiled verilator with MinGW, and ran: @verilator.exe -Wno-lint -Wno-UNOPTFLAT -language 1364-2001 --trace --compiler msvc --cc top.v@
There are some small issues that were easy to solve:
However there are two bigger issues:
When trying to compile top.cpp I get a false "undeclared identifier" error reported on some very long signals.
A possible solution could be defining sub structs for each hierarchy level instead of using DOT. Another solution could be truncating these names somehow and adding some unique suffix.
In the meantime I was able to work around these two issues by modifying the Verilog files and the cpp files generated by Verilator. However, it would be easier and cleaner having these problem fixed in Verilator.
Thanks,
Amir
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