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The order of packed dimensions is backwards #213

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veripoolbot opened this issue Jan 26, 2010 · 1 comment
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The order of packed dimensions is backwards #213

veripoolbot opened this issue Jan 26, 2010 · 1 comment
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resolution: fixed Closed; fixed

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Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 213 from https://www.veripool.org
Original Date: 2010-01-26
Original Assignee: Wilson Snyder (@wsnyder)

A signal defined as

logic [2:0] [31:0]  data_in;

should contain three elements of 32-bits each. In Verilator it creates 32 elements of 3-bits each. The patch attached shows this in t/t_mem_packed and has been tested in another simulator.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-26T13:08:16Z

Wow, sorry the original test wasn't covering it well.

Fixed in git, thanks for the tests as always.

@veripoolbot veripoolbot added the resolution: fixed Closed; fixed label Dec 22, 2019
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