You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 213 from https://www.veripool.org
Original Date: 2010-01-26
Original Assignee: Wilson Snyder (@wsnyder)
A signal defined as
logic [2:0] [31:0] data_in;
should contain three elements of 32-bits each. In Verilator it creates 32 elements of 3-bits each. The patch attached shows this in t/t_mem_packed and has been tested in another simulator.
The text was updated successfully, but these errors were encountered:
Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 213 from https://www.veripool.org
Original Date: 2010-01-26
Original Assignee: Wilson Snyder (@wsnyder)
A signal defined as
should contain three elements of 32-bits each. In Verilator it creates 32 elements of 3-bits each. The patch attached shows this in t/t_mem_packed and has been tested in another simulator.
The text was updated successfully, but these errors were encountered: