Bitwise reductions on signals with >1 packed dimension generates incorrect code #227
Labels
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
resolution: fixed
Closed; fixed
Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 227 from https://www.veripool.org
Original Date: 2010-03-23
Original Assignee: Byron Bradley (@bbradley)
Code such as:
gets treated as a normal slice and generates incorrect code. I have this working and will submit patches tomorrow, just need to do some more verification. The changes are mostly to V3Slice with some small changes elsewhere to differentiate between packed and unpacked dimensions.
The text was updated successfully, but these errors were encountered: