Author Name: David Rogoff
Original Redmine Issue: 245 from https://www.veripool.org
Original Date: 2010-04-18
Original Assignee: Wilson Snyder (@wsnyder)

Hi Wilson.

I asked for this a year ago as along with the modport stuff you added (thanks!) in Issue #75. As I, and other engineers I work with, have done a ton more SV code, I'm going to ask again, since it would really help in spotting renaming of signals through hierarchies.

Original request:

Use, if specified (SVD variable??) .name port connections for any port connected to a signal with the same name, which would be anything in AUTOINST not using a template:

module top;
    myram myram0(
     /*AUTOINST*/
       // Interfaces
       .ram_if        (ram_if.slave),

       // Inputs
       .clk,
       .reset);

This is nice because it makes it obvious which ports connect to signals that have a different name. Of course you can just use .*, but I've threatened to shoot anyone in my group who uses that since it makes code totally unreadable.

You replied

I don't want to do this (yet) because it would break Verilog 2001 files, and there's no reliable way to tell which language is in use. Also, it would mess up AUTOWIRE.

I'd suggest again, that this could be a config variable for verilog-mode to enable.

Thanks,

David