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Author Name: Evgeni Stavinov
Original Redmine Issue: 256 from https://www.veripool.org
Original Date: 2010-05-27
Original Assignee: Wilson Snyder (@wsnyder)
When running vhier on the code with "myreg <= #`FFDLY 'b0;" Verilog notation, I'm getting the following error:
%Error: /mypath/myfile.v:some_line: syntax error, unexpected ';', expecting CLASS-IDENTIFIER or COVERGROUP-IDENTIFIER or TYPE-IDENTIFIER
The code is:
define FFDLY 100 always @(posedge clk) begin if (reset) begin myreg1 <= #FFDLY 7'd0;
myreg2 <= #`FFDLY 'b0;
....
No other synthesis and sim tool has a problem with that.
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-05-27T18:09:59Z
Wow, you're right.
Looking at the spec, the leading hash means "# 1 'b0" must be interpreted as "# 1" then "'b0" while if the leading "#" wasn't there it would be "1'b0". Ditto any other place a integer can appear "next to" a based number. Thus numbers can't be determined standalone without knowing the context. That's a really nasty thing for any language standard to require.
Let me think about this. Meantime, use #(FFDLY) or #FFDLY 1'b0.
Author Name: Evgeni Stavinov
Original Redmine Issue: 256 from https://www.veripool.org
Original Date: 2010-05-27
Original Assignee: Wilson Snyder (@wsnyder)
When running vhier on the code with "myreg <= #`FFDLY 'b0;" Verilog notation, I'm getting the following error:
%Error: /mypath/myfile.v:some_line: syntax error, unexpected ';', expecting CLASS-IDENTIFIER or COVERGROUP-IDENTIFIER or TYPE-IDENTIFIER
The code is:
define FFDLY 100 always @(posedge clk) begin if (reset) begin myreg1 <= #
FFDLY 7'd0;myreg2 <= #`FFDLY 'b0;
....
No other synthesis and sim tool has a problem with that.
The text was updated successfully, but these errors were encountered: