Author Name: Laurent Lefebure
Original Redmine Issue: 257 from https://www.veripool.org
Original Date: 2010-06-01
Original Assignee: Wilson Snyder (@wsnyder)

Hi Wilson,
First of all, thank you for this great package!
I am dealing with netlist gate and note verilog. My aim is to perform quick consistency checks on netlist I am receiving. I want to treat the netlist only without any library informations.
The issue is when parsing the netlist, it drops all cell instances which have no definitions (as I don't have verilog librariesfor them). I would like to have a way to specify the parser to keep them and puts the input/output as undefined direction (or by specifying a list of pattern for inputs and outputs it will know what is an input or an output). There is link_read_nonfatal which will disable error message, here I would like something similar to control wether to drop or not undefined cells and to specify input/output pattern list.
Do you see a way to do so?

Thanks and best regards,
Laurent Lefebure