Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Feature Request: Autoformat/indent Verilog 2001 Module Headers #260

Closed
veripoolbot opened this issue Jun 4, 2010 · 2 comments
Closed

Feature Request: Autoformat/indent Verilog 2001 Module Headers #260

veripoolbot opened this issue Jun 4, 2010 · 2 comments
Labels
indents

Comments

@veripoolbot
Copy link
Collaborator

Author Name: Joachim Lechner
Original Redmine Issue: 260 from https://www.veripool.org
Original Date: 2010-06-04
Original Assignee: Michael McNamara

It would be nice to have the autoformat/indent feature also for verilog 2001 module headers.

e.g.:

module test_module(
  input wire [1:0]      pin1,
  input wire      pin2,
  input wire [1:0]      pin3,
  input wire        pin4,
  output wire     pin5,
  output wire [10:0] pin6,
  output reg     pin7,
  output reg  [1:0]     pin8
  );

to something like:

module test_module(
  input  wire [1:0]  pin1,
  input  wire        pin2,
  input  wire [1:0]  pin3,
  input  wire        pin4,
  output wire        pin5,
  output wire [10:0] pin6,
  output reg         pin7,
  output reg  [1:0]  pin8
  );

Best regards, Joachim
@veripoolbot
Copy link
Collaborator Author

Original Redmine Comment
Author Name: Joachim Lechner
Original Date: 2010-06-04T07:32:07Z

Sorry now the example should be readable - see attached file.

@veripoolbot
Copy link
Collaborator Author

Original Redmine Comment
Author Name: Michael McNamara
Original Date: 2011-02-21T06:46:28Z

Fixed with version 666 (oooh!) declarations are lined up inside modern style port declaration blocks.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
indents
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@veripoolbot