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Keeping 'defparam' statements in a Netlist parsed by Verilog::Netlist #261

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veripoolbot opened this issue Jun 4, 2010 · 2 comments
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Keeping 'defparam' statements in a Netlist parsed by Verilog::Netlist #261

veripoolbot opened this issue Jun 4, 2010 · 2 comments
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Author Name: Pierre-David Pfister
Original Redmine Issue: 261 from https://www.veripool.org
Original Date: 2010-06-04
Original Assignee: Wilson Snyder (@wsnyder)

Hi,
I'm new to the Verilog-Perl package. We have an FPGA netlist which contains 'defparam' statements. Is it possible to keep them when using the Verilog-Perl package, and output them after some netlist changes? How?
Thanks,
Pierre

Sample input code:

defparam iSYSRESETn_cZ.lut_mask=64'hffff00ffff000000;
defparam iSYSRESETn_cZ.shared_arith="off";
defparam iSYSRESETn_cZ.extended_lut="off";
// @143:706
  stratixii_lcell_comb iPORESETn_cZ (
	.combout(iPORESETn),
	.sumout(),
	.cout(),
	.dataf(PORESETnQQ),
	.datae(PORESETn),
	.datad(RSTBYPASS),
	.datac(VCC),
	.datab(VCC),
	.dataa(VCC),
	.datag(VCC),
	.cin(GND),
	.sharein()
);
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-06-08T23:36:34Z

Good idea, added to git for next release, 3.242+.

This creates ::Defparam objects, which the write_verilog routine will spit back out. The main ugly thing is I don't parse the cell the defparams are connected to, you'll need to do that yourself.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-06-21T23:46:47Z

In 3.250.

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