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Author Name: Evgeni Stavinov
Original Redmine Issue: 262 from https://www.veripool.org
Original Date: 2010-06-08
Original Assignee: Wilson Snyder (@wsnyder)
The following port declaration causes an error: "unexpected '{'. expecting CLASS-IDENTIFIER..."
Author Name: Evgeni Stavinov
Original Redmine Issue: 262 from https://www.veripool.org
Original Date: 2010-06-08
Original Assignee: Wilson Snyder (@wsnyder)
The following port declaration causes an error: "unexpected '{'. expecting CLASS-IDENTIFIER..."
module my_module ( Y, {A1, A2} , B, psup, nsup );
output Y;
input A1, A2, B;
input psup, nsup;
...
This is according to the Verilog specification of complex module ports.
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