*** verilog-mode.el	2010-07-14 17:29:54.201890000 -0500
--- -	2010-07-14 17:34:41.068421000 -0500
***************
*** 1017,1022 ****
--- 1017,1029 ----
     :type 'string)
  (put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
  
+ (defcustom verilog-auto-tieoff-ignore-regexp nil
+   "*If set, when creating AUTOTIEOFF list, ignore signals matching this regexp.
+ See the \\[verilog-faq] for examples on using this."
+   :group 'verilog-mode-auto
+   :type 'string)
+ (put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
+ 
  (defcustom verilog-typedef-regexp nil
     "*If non-nil, regular expression that matches Verilog-2001 typedef names.
  For example, \"_t$\" matches typedefs named with _t, as in the C language."
***************
*** 10821,10826 ****
--- 10828,10836 ----
  Signals that match `verilog-active-low-regexp' will be deasserted by tieing
  them to a one.
  
+ You can add signals you do not want included in AUTOTIEOFF with
+ `verilog-auto-tieoff-ignore-regexp'.
+ 
  An example of making a stub for another module:
  
       module ExampStub (/*AUTOINST*/);
***************
*** 10863,10868 ****
--- 10873,10880 ----
  			      (verilog-decls-get-gparams moddecls)
  			      (verilog-subdecls-get-outputs modsubdecls)
  			      (verilog-subdecls-get-inouts modsubdecls)))))
+       (setq sig-list (verilog-signals-not-matching-regexp
+ 		      sig-list verilog-auto-tieoff-ignore-regexp))
         (when sig-list
  	(forward-line 1)
  	(verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")