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Author Name: Scott Roland
Original Redmine Issue: 271 from https://www.veripool.org
Original Date: 2010-07-21
Here is a collection of indentation issues I see with Revision 629
// This is an example file to show the indentation errors I see with
// the verilog-mode.
// The assumption is that this file will be included into another
// file defining a module.
initial begin
int unsigned count = 0;
int value; // ERROR #1: value should align with count
string source_str;
end
task begin_trans // ERROR #2 task should align with end
(input int h_stream ///<[in ] Handle of the stream to use
);
endtask : begin_trans
//////////////////////////////////////////////////////////////////////
// ERROR #3 Doxygen inline comment should not cause this indent
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-07-21T10:42:41Z
Thanks for the report.
Mac, BTW I was going to argue the task is indented properly and it's the initial that is improper, but now that tasks and functions can now be global in SV I guess it makes sense they can be at column zero.
Also, one hackaround is this:
`ifdef NEVER
module just_for_emacs;
`endif
initial ...
Author Name: Scott Roland
Original Redmine Issue: 271 from https://www.veripool.org
Original Date: 2010-07-21
Here is a collection of indentation issues I see with Revision 629
The text was updated successfully, but these errors were encountered: