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Verilog-mode module parameter indentation #273

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veripoolbot opened this issue Jul 27, 2010 · 1 comment
Closed

Verilog-mode module parameter indentation #273

veripoolbot opened this issue Jul 27, 2010 · 1 comment
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@veripoolbot
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Author Name: Tony Keiser
Original Redmine Issue: 273 from https://www.veripool.org
Original Date: 2010-07-27
Original Assignee: Michael McNamara


I have noticed an indentation problem in verilog-mode v.631 on emacs 23.1 and 23.2 when using this particular style to
define and set default values for module parameters. The OS is Windows 7 64-bit.

module ui_wr_data #
  (
  parameter TCQ = 100,
		parameter APP_DATA_WIDTH       = 256,
			parameter APP_MASK_WIDTH       = 32,
				parameter ECC                  = "OFF",
					parameter ECC_TEST             = "OFF",
						parameter CWL                  = 5
																						 )
	(/*AUTOARG*/
																						 // Outputs
																						 app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
							raw_not_ecc,
							// Inputs
							rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
							app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
							ram_init_done_r, ram_init_addr
																						 );


@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-11-29T15:45:19Z


This was fixed some time ago.

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