------------------------------ my_sv_if.sv --------------------------------
interface my_sv_if
  logic a;
  logic b;
  modport master_mp(input a, output b);
  modport slave_mp(output a, input b);
  modport monitor (input a, input b);
endinterface

-------------------------------- my_tb.sv ---------------------------------
module my_tb;
  my_if inst_if (/*AUTOINST*/);
endmodule

---------------------------------------------------------------------------

"verilog-modi-lookup: biu_tb.v:738: Can't locate my_if module definition
     Check the verilog-library-directories variable.
     I looked in (if not listed, doesn't exist):
	< some path >
	< some path /my_if.sv >"