Author Name: Pihay Saelieo
Original Redmine Issue: 275 from https://www.veripool.org
Original Date: 2010-08-02
Original Assignee: Wilson Snyder (@wsnyder)

It looks like the verilog parser does not understand split-bus syntax in the port declaration section of the module header. Our simulation tools, however, can parse this syntax without issues.

For example, the parser will error out when reading the following snippet:

module tb (
OUT1,
{OUT2[1], OUT2[0]}, // Error on this line
IN );
output OUT1;
output [1:0] OUT2;
input [2:0] IN;
endmodule

Attached is a more detailed testcase showing this. Please execute the "read_verilog" script in the same directory as the "sense_q.v" file. The error message is:
%Error: sense_q.v:18: syntax error, unexpected '{', expecting "CLASS-IDENTIFIER" or "COVERGROUP-IDENTIFIER" or "TYPE-IDENTIFIER"