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verilog text does not print port direction for V2001 input code #278

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veripoolbot opened this issue Aug 16, 2010 · 1 comment
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Author Name: Mike Z
Original Redmine Issue: 278 from https://www.veripool.org
Original Date: 2010-08-16
Original Assignee: Wilson Snyder (@wsnyder)


Reading in a Verilog 2001 file.. just the top level module (not its sub modules)

mod->dump shows that that ports are known with direction

printing the verilog_text results in an output file with no port direction

I believe IT installed Verilog-Perl-3.240 from CPAN

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-08-16T15:46:41Z


Ah, I see now the difference. You need to call $netlist->link after reading and before calling verilog_text as this creates some references needed for the dumping to work. I've updated the documentation for the next release.

BTW I don't know what your "AUTOGEN" is, but you may want to take a look at the Verilog-Mode for Emacs AUTOINST/AUTOWIRE interconnection system. It may do what you need in a more supported and industry-wide way.

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